;*********************************************************************
;
;
; Controller AT90S1200
;
; Definitions for various registers and bits
; for generic program
;
; Adapted from Atmel code
; Richard Hosking
; Rev 1
; 27/12/99
;
;***** Specify Device
.device AT90S1200
;***** I/O Register Definitions
.equ SREG =$3f ; Status register
.equ GIMSK =$3b ;General Interrupt mask register
.equ TIMSK =$39 ;Timer/counter interrupt mask register
.equ TIFR =$38 ;Timer/counter interrupt flag register
.equ MCUCR =$35 ;MCU control register
.equ TCCR0 =$33 ;Timer/counter control register
.equ TCNT0 =$32 ;Timer/counter
.equ WDTCR =$21 ;Watcdog control reg
.equ EEAR =$1e ;EEPROM address reg
.equ EEDR =$1d ;EEPROM data reg
.equ EECR =$1c ;EEPROM control reg
.equ PORTB =$18 ;Port B
.equ DDRB =$17 ; Port B data direction reg 1=out 0=in
.equ PINB =$16 ;Port B input pins direct
.equ PORTD =$12 ;Port D
.equ DDRD =$11 ;
.equ PIND =$10 ;
.equ ACSR =$08 ; Analog comparator control/status reg
;***** Bit Definitions
; STATUS REG
.equ GIE =7 ; Global Interupt Enable in STATUS reg
.equ BCS =6 ; Bit Copy Storage - bld command (bit load)
; writes a specified bit from a register
; to this bit - bst (bit store) writes this bit
; to the specified register
.equ H =5 ; Half carry flag
.equ HALF_CARRY =5
.equ S =4 ; Sign bit
.equ V =3 ; Twos complement overflow flag
.equ N =2 ; Negative flag
.equ NEG =2
.equ Z =1 ; Zero flag
.equ ZERO =1
.equ C =0 ; Carry flag
.equ CARRY =0
;*************
.equ INT0 =6 ; Ext interrupt D6
.equ TOIE0 =1 ;Timer/counter overflow interrupt enable
; bit 1 in TIMSK enable high
.equ TOV0 =1 ; Timer/counter overflow flag bit 1 in TIFR
; high = overflow
.equ SE =5 ; Sleep enable (1) in MCUCR
.equ SM =4 ; Sleep mode 0=idle 1= power down in MCUCR
.equ ISC01 =1 ; Interrupt sense control in MCUCR
.equ ISC00 =0 ; 00 INT0 low generates interrupt
; 01 reserved
; 10 falling edge of INT0 -> interrupt
; 11 rising edge of INT0 -> interrupt
.equ CS02 =2 ; CS00-CS02 Clock select bits for timer
.equ CS01 =1 ; Set prescaler/ clock source
.equ CS00 =0 ; (prescaler/external source)
.equ WDE =3 ; In watchdog control reg Watchdog enable (1)
.equ WDP2 =2 ; WDP0-WDP2 in watchdog control reg
.equ WDP1 =1 ; set watchdog timeout approx 16-2000 msec
.equ WDP0 =0
.equ EEWE =1 ; EEPROM write enable bit in EECR set to write data
; cleared by hardware when write cycle complete (2.5 ms)
.equ EERE =0 ; EEPROM read enable set to read data
; when bit is cleared by hardware requested data is in EEDR
.equ ACD =7 ; Analog comparator disable in ACSR 1= comparator off
.equ ACO =5 ; Analog comparator output
.equ ACI =4 ; Analaog comparator interrupt flag
.equ ACIE =3 ; Analog comparator interrupt enable 1= enabled
.equ ACIS1 =1 ; ACIS0-ACIS1 AC interrupt mode select
.equ ACIS0 =0
.equ INT0addr=$001 ;External Interrupt0 Vector Address
.equ OVF0addr=$002 ;Overflow0 Interrupt Vector Address
.equ ACIaddr =$003 ;Analog Comparator Interrupt Vector Address
